As software defines the development of network, for making data processing at the network level more scalable, network function processing applications based on software in traditional X86 servers have become increasingly popular. Compared to the traditional hardware-based network middleware (MiddleBox), these software-based network functions are more scalable, cost saving and easy to deploy.
The modern datacenters usually have a bandwidth of 10 Gbps-40 Gbps, and some datacenters even operate with a bandwidth up to 100 Gbps. In data link of 10 Gbps, for maximizing the throughput, processing a 64 Byte data packet takes 67.2 ns. Software-based network function applications rely on central processing units (CPUs) to process data packets. Since a CPU is typically designed for general purpose computation, a simple packet operation, such as layer 3 packet forwarding, takes about 75 CPU cycles (approximately 34 ns). In such case, the computing capacity of the CPU may be sufficient. However, a complicated packet operation, such as packet encryption, can take about 2300 clock cycles (approximately 950 ns), and thus requires plural CPU cores to work together for optimal performance. For a greater link bandwidth, such as 40 Gbps, or even 100 Gbps, the number of required CPU cores may be much greater than what a single server can afford.
Therefore, realizing network functions on FPGAs (Field Programmable Gate Arrays) has been proposed as a solution. FPGAs are advantageously reconfigurable. By dynamically configuring the logic combinations of their gate arrays, different hardware functions can be realized. FPGAs have the advantages of low energy consumption and high performance. Nevertheless, the prior art fails to make the best use of FPGA resources, resulting in limited actual utilization level.